In recent years, with the expansion of the digital signal processing field, a digital signal processor (hereinafter, referred to as a DSP) has found broad application in equipment such as mobile communication equipment. Such equipment is driven with a battery. Therefore, reduction of the power consumption of the DSP is strongly desired. In a DSP, in general, instructions are read from a built-in memory or a memory externally connected to the DSP, which stores a program in advance, and an instruction decoder decodes the instructions and outputs various control signals to a processing unit such as an arithmetic logic unit (ALU).
FIG. 13 is a block diagram showing a configuration of a portion of a conventional DSP related to decoding of instructions. When instructions are to be read from a built-in memory 92 and executed, a program counter 91 outputs addresses to the memory 92, and the memory 92 outputs instructions stored at the input addresses to an instruction decoder 93. The instruction decoder 93 decodes the input instructions, produces various control signals as decoded results DC and outputs the signals to a processing unit 94. The processing unit 94 executes operations such as addition and subtraction, for example, according to the decoded results DC.
When instructions are to be read from an externally connected memory 97, the program counter 91 outputs addresses to the memory 97 via a pad 95, and the memory 97 outputs instructions stored at the input addresses to the instruction decoder 93 via a pad 96. The instruction decoder 93 decodes the input instructions and outputs the decoded results DC to the processing unit 94, as in the case of reading instructions from the memory 92.
FIG. 2 is a view illustrating an example of the structure of an instruction input into the instruction decoder 93. The highest-order field is used to specify the type of operation or data transfer, and the subsequent field is used to specify the type of register into which data is written. The next two fields are used to specify the type of register from which data is read (see “MN1920 Series LSI Manual”, Matsushita Electronics Corporation, p. 2—2, 1990, for example).
Problem to be Solved
In execution of a program with the DSP having the above configuration, different instructions are sequentially input into the instruction decoder 93. Every time such instructions are input, the potential of the lines and the pad 96 on the route from the memory 92 or 97 to the instruction decoder 93 changes from a low potential “L” to a high potential “H”, or from “H” to “L”. In general, in an LSI of a CMOS (complementary metal oxide semiconductor) structure, the operating current is highest when the potential of a signal changes. Accordingly, the power consumption in decoding of an instruction is greater as a larger number of bits of an instruction input into the instruction decoder 93 changes in value.
In an information processing device such as a DSP that is incorporated in an apparatus, a program will not be changed normally once details of processing are determined and the device is incorporated in an apparatus. The DSP performs processing steps sequentially according to the program. In many cases, the types of instructions executed in a given processing step are limited. Even in such cases, however, the DSP is prepared to be adaptive to execution of all instructions, and there has been made no attempt of changing the width of the instruction field and the allocation of instruction codes.